Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and like type programmable elements. The CLBs and IOBs are interconnected by a programmable interconnect structure. An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. Notably, an FPGA may include one or more embedded processors. The programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The bitstream is typically stored in an external nonvolatile memory, such as an erasable programmable read only memory (EPROM). The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured.
Manufacturers typically provide device models of their PLDs for use with computer aided design (CAD) software. For example, CAD software can use a device model during simulation or other analysis of designs (e.g., timing analysis), as well as for implementation of designs (e.g., placement and routing). One type of attribute included in a device model for various PLD components is delay. Various types of delays may be modeled, such as propagation delay, setup and hold delays, minimum pulse width requirements, and the like. For example, propagation delay can be associated with a path between terminals of a component (“delay path”) and can be defined as the length of time it takes the input of the signal path to affect the output of the signal path. A setup and hold delay can be associated with a delay path between the data input pin to the clock pin. A device model for a PLD may include various delays associated with various components therein, such as flip-flops, lookup tables (LUTs), dedicated logic blocks, and the like.
In present device models, the definition of a delay (“delay definition”) can be separated from the value of the delay (“delay value”). This allows the delay values to be included in a separate file (sometimes referred to as a “speed file”) from the rest of the device model, which can be included in one or more “definition files”. Delay values typically change more often than other delay attributes and thus it is desirable to store the delay values in a separate speed file. Thus, the delay values in the device model can be updated merely by updating the speed file. For example, a flip-flop may include a delay definition identified by a name “FF_DELAY”. The speed file may include an entry “FF_DELAY 1.2”, which indicates a delay value of 1.2 time units (the delay value units can be microseconds, nanoseconds, picoseconds, etc., depending on technology).
One problem with the above approach arises when two instances of a component require different delay values. Since a component is associated with a particular delay definition name, one instance of the component cannot have a different delay value than another instance. If it is discovered a particular instance of a component requires a different delay value than other instance(s), designers must: (1) create a new component that duplicates the definition of the old component except for a new delay definition name; (2) create a new delay definition name for the new component; (3) change the instance of the component to be an instance of this new component; (4) add a delay value for this new delay definition in the speed file; and (5) distribute new definition and speed file(s) to customers. Such a change can be an expensive and difficult process.